
PIC18FXX39
DS30485A-page 142
Preliminary
2002 Microchip Technology Inc.
FIGURE 16-10:
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SS
PI
F
BF
(
S
SPS
TA
T
<
0
>
)
S
12
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
12
3
4
5
7
8
9
P
1
0
A
9
A
8
A
7
A
6
A
5
A
4A
3A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
1
D
0
Re
ce
iv
eDa
ta
Byte
ACK
R/W
=
0
ACK
Re
ceive
F
irs
tB
yte
of
A
d
dr
ess
C
lea
re
di
n
s
o
ft
w
a
re
D2
6
(P
IR
1<
3>
)
C
lear
ed
in
so
ftw
are
R
e
ce
iv
eS
econd
B
yte
of
A
ddre
ss
C
le
a
red
by
har
dw
are
w
hen
S
P
A
D
is
update
d
w
ith
lo
w
byte
of
add
ress
UA
(
S
PST
A
T
<1
>)
Cl
ock
is
h
e
ld
lo
w
u
n
til
updat
e
of
S
P
A
D
has
ta
ken
pl
ac
e
UA
is
set
indicat
in
g
tha
t
the
S
P
A
D
need
sto
be
upda
ted
UA
is
set
in
dicating
that
S
P
A
D
need
sto
be
up
d
a
ted
C
le
ar
ed
by
har
dw
are
w
hen
SSP
ADD
is
u
p
d
ate
d
with
h
ig
h
by
te
of
addr
ess
S
SPB
UF
is
wr
itte
nwi
th
conten
ts
o
fS
S
P
S
R
D
um
m
y
re
a
do
fSS
PBUF
to
clear
B
F
flag
AC
K
CKP
12
3
4
5
7
8
9
D7
D6
D5
D4
D3
D1
D0
Re
ce
ive
Da
ta
B
yte
B
us
M
a
ste
r
term
inates
tran
sfer
D2
6
ACK
Cle
a
re
d
in
so
ftwa
re
Cle
a
re
d
in
so
ftw
ar
e
SSP
O
V
(
S
SPCO
N
<
6>
)
S
SPO
V
is
s
et
b
e
ca
u
se
S
SPB
UF
is
stil
lf
u
ll.
AC
K
is
no
tsent.
(C
K
P
do
es
not
reset
to
‘0
’w
hen
S
E
N
=
0)
Clo
ck
is
h
e
ld
lo
w
u
n
til
upda
te
of
S
P
A
D
has
ta
ken
p
la
ce